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IR3863MPBF
CIRCUIT DESCRIPTION
UNDER/OVER VOLTAGE MONITOR
The IR3863 monitors the voltage at the FB node
through a 350ns filter. If the FB voltage is below
OVER CURRENT MONITOR
The over-current circuitry monitors the output
current during each switching cycle. The voltage
the under voltage threshold, UV# is set to LOW
across
the
lower
MOSFET,
VPHASE,
is
holding PGOOD to be LOW. If the FB voltage is
above the over voltage threshold, OV# is set to
LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD
signal is pulled low. Toggling VCC or EN will
allow the next start up. Figure 21 and 22 show
monitored for over current and zero crossing. The
OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower
MOSFET is gated on. This delay functions to filter
out switching noise. The minimum lower gate
interval allows time to sample VPHASE.
PGOOD
status
change
when
UV/OV
is
detected. The over voltage and under voltage
thresholds can be found in the Electrical
Specification section.
The over current trip point is programmed with a
resistor from the ISET pin to PHASE pin, as
shown in equation 4. When over current is
detected, the MOSFET gates are tri-state and SS
voltage is pulled to 0V. This initiates a new soft
start cycle. If there is a total of four OC events, the
IR3863 will disable switching. Toggling VCC or
EN will allow the next start up.
R SET ?
R DSON ? I OC
19 ? A
(4)
* typical filter delay
Figure 21. Under/Over Voltage Monitor
Figure 23. Over Current Protection
UNDER VOLTAGE LOCK-OUT
The IR3863 has VCC and EN under voltage lock-
out (UVLO) protection. When either VCC or EN is
* typical filter delay
below their UVLO threshold, IR3863 is disabled.
IR3863 will restart when both VCC and EN are
above their UVLO thresholds.
Figure 22. Over Voltage Protection
8/8/2012 Rev3.2
12
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